1. Field of the Invention
The present invention relates to a time division switching apparatus, and particularly to an improvement in a time division switching apparatus which collectively performs, for example, the interchange of a bit unit and that of a time slot unit, and especially carries out the interchange of digital data.
2. Description of the Prior Art
FIG. 1 shows the construction of a time division switching apparatus which performs a digital data exchange illustrated, for example, in FIG. 1.33 on page 43 of the technical magazine entitled "Simple Digital Data Exchange (Yasashii Digital Koukan)" published by Ohm Co., Ltd. In the same drawing, there are shown a time division switching apparatus 100, a counter 114, a control memory 115, a buffer memory 111, an input highway 150, an output highway 160, a reference pulse 170, a clock 180, a value 190 to be counted, which is used as an address to be inputted to each of the buffer memory 111 and the control memory 115, and an output 200 from the control memory 115, i.e., a control memory output.
FIG. 2 is a timing chart for describing the operation for writing data received from the input highway 150, i.e., on the input highway 150 into the buffer memory 111 provided in the time division switching apparatus 100 shown in FIG. 1. FIG. 3 is a timing chart for describing the operation for reading data from the buffer memory 111 to the output highway 160.
Referring to FIGS. 2 and 3, symbols t.sub.1, t.sub.2, . . . indicate time positions. A description will next be made on the operation of this apparatus. In FIG. 1, the counter 114 is reset by the reference pulse 170 which is periodically repeated. The counter 114 also serves to produce the counted value 190 in step-by-step operation based on the clock 180 until it is reset by the following reference pulse 170 so as to supply the same to the buffer memory 111 and the control memory 115. Then, the buffer memory 111 serves to write data on the input highway 150 into an address designated by the counted value 190, and the control memory 115 supplies the data, which have been written into the address designated by the counted value 190, as a control memory output 200, to the buffer memory 111. Further, the buffer memory 111 serves to read out data from an address designated by the control memory output 200 so as to supply the read data to the output highway 160.
A description will now be made on the operation timing referred to above. Referring to FIG. 2, data of A, B, C, D and E on the input highway 150 are written into a buffer memory in which #0, #1, #2, . . . constituting the counted value 190 as output values from the counter 114 are taken as addresses. Referring to FIG. 3, the counted value 190 from the counter 114 corresponds to #0 at the time position t.sub.1. Then, the control memory 115 produces the count value #1, which has been written into an address #0, thereof, as the output 200. The buffer memory 111 produces data, which have been written into address #1, in response to the control memory output 200 as an address. Since data B have been written into an address #1 in the buffer memory 111, as shown in FIG. 2, the data B are outputted at the time position t.sub.1 in FIG. 3 where the reference pulse 170 shown in FIG. 3 is a pulse at a position delayed from the reference pulse 170 shown in FIG. 3 by one cycle. Similarly, the buffer memory 111 outputs data A, which have been written into an address #0, thereof, at the time position t.sub.2. Similarly, any one of data is also outputted at the time positions t.sub.3, t.sub.4 and t.sub.5 by performing the same operation as referred to above.
FIG. 4 is a diagram illustrative of the connection of transmission devices 1081, 1082 to an input highway 150 and an output highway 160 respectively. A description will now be made to the data exchange with reference to FIG. 4.
In FIG. 4, for example, the transmission device 1081 serves to output data A to the input highway 150 at the time position t.sub.1 shown in FIGS. 2 and 3, and receive data from the output highway 160 at the same time position, while the transmission device 1082 serves to output data B to the input highway 150 at the time position t.sub.2, and receive data from the output highway 160 at the same time position. When the time division switching apparatus 100 operates to execute the exchange of data at such time positions as shown in FIGS. 2 and 3, the transmission device 1081 serves to receive the data B outputted from the transmission device 1082 whereas the transmission device 1082 serves to receive the data A outputted from the transmission device 1081. Thus, the exchange between the data A and B is made, so that the data exchange is performed between the transmission devices 1081 and 1082.
Since the conventional time division switching apparatus is constructed as described above, necessary measures such as an increase in the operation frequency of the time division switching apparatus should be taken depending on an increase in the quantity of data to be exchanged within a given period of time or reduction in the capacity of data units such as a frame unit, an octet unit, a bit unit, etc. In addition, since the buffer memory and the control memory provided in the time division switching apparatus each make use of memory circuits, the limit of the operation frequency of each memory circuit is lower than that of the operation frequency of another circuit. Thus, a restriction is imposed on the quantity of data to be exchanged and the data units owing to the limit of the operation frequency of each of the buffer memory and the control memory.
Further, when a plurality of input highways and output highways are employed in the apparatus, such a circuit construction as shown in FIG. 5 is usually taken.
In other words, a multiplexer 1091 serves to convert data on each of input highways 150a, 150b, . . . , 150n into data represented in a multiplex form so as to apply the resultant data to a high-speed highway 1501. Then, the time division switching apparatus 100 serves to convert the data on the high-speed highway 1501 on a time-sharing basis into a desired data so as to apply the result to a high-speed highway 1601. A demultiplexer 1092 serves to separate data on the high-speed highway 1601 into individual data so as to supply the same to corresponding output highways 160a, 160b, . . . 160n. At this time, the data transfer frequency of each of the input highways 150a, 150b, . . . , 150n is equal to that of each of the output highways 160a, 160b, . . . , 160n. The data transfer frequency of each of both the high-speed input highway 1501 and the high-speed output highway 1601 is equal to the sum of the input highways 150a , 150b, . . . , 150n or the output highways 160a, 160b, . . . , 160n.
Accordingly, the time division switching apparatus 100 must be activated at the frequency equal to the total data transfer frequency of the input highways 150a, 150b, . . . , 150n or the output highways 160a, 160b, . . . , 160n. Besides, an upper limit is taken for the operation frequency of each of circuits such as a memory circuit, etc. employed in the time division switching apparatus 100, so that limitations are imposed on the number of highways which are containable.
FIG. 6 is a timing chart showing an example in which read/write for the buffer memory 111 is performed in the former half or later half of a time slot, in the case when both data on input highway 150 and on output highway 160 in FIG. 1 are an 8-bit parallel data, and shows an example in which data on the input/output highways are multiplexed in the form of 32 words by 8 bits per word, where F represents a frame, TS a time slot, R a read period and W a write period. The counter 114 will produce addresses of 0-31 in the buffer memory 111 within a time interval corresponding to one frame F. At this case, the buffer memory 111 is set in the form of 32 words by 8 bits whereas the control memory 115 is constructed in the form of at least 32 words by 5 bits.
Information of 000-007 represented in the form of 8 bits on the input highway is applied as one word to the buffer memory 111. Where the sequential write and random read system is employed during the read period R corresponding to the first half of one time slot TS, a selector serves to select a desired address out of addresses read from the control memory 115 and apply the same as a reading address for the buffer memory 111 thereto. Thereafter, 8-bit information read from the buffer memory 111 is delivered to the output highway. During the write period W corresponding to the latter half of said one time slot TS, the selector serves to select a desired output out of outputs from the counter 114 and then apply the same as a writing address for the buffer memory 111 thereto. Then, the 8-bit information of 000-007 on the input highway is written into, for example, a location 0.
During the period of the following time slot, an address read from the control memory 115 during the read period R is read from the buffer memory 111 as a reading address. 8-bit information of 010-017 on the input highway is written into, for example, a location 1 in the buffer memory 111, taking an output from the counter 114 as a writing address.
The principle of the interchange of data is same as the principle thereof in FIG. 1, FIG. 2 and FIG. 3.
Where the switching of data between one bit units is performed using the above-described conventional time division switching apparatus, each memory is constructed in the form of 256 words by one bit. Since the control memory 115 is constructed in the form of 256 words by 8 bits, it is necessary to perform the high-speed operation of eight times the access speed as compared with the case where 8-bit parallel access (access of the time slot unit) is executed. In the time division switching apparatus in which the switching of one bit units has been constructed as a criterion, where it is desired to perform the interchange of the time slot unit, it is necessary to set or incorporate address information corresponding to 8 bits into the control memory 115, thereby causing a problem that a lot of time is required to establish each of switches for performing the interchange of the time slot unit.